In memory devices, such as EEPROMS, a unit of information is stored in a floating-gate transistor. Depending on the logic state to be stored (i.e., a logic 0 or a logic 1), a positive or negative electrical charge is trapped in the floating gate of the transistor, thus altering its threshold. If no electrical charges are stored in the floating gate, the memory cell is termed virgin, otherwise it is deleted or written.
The correspondence between the deleted or written logic states depends on conventions which can change from product to product. The logic state of the cell is recognized on the basis of the current that flows across it in very specific bias conditions. If a negative charge is trapped in the floating gate of the transistor, the threshold of the cell is higher than in a virgin cell. Otherwise, the threshold is lower than in a virgin cell.
In most cases, the information is obtained from a comparison between the current of the cell and the current of an appropriate reference, which can be absolute (a constant current) or derived from a virgin cell which is biased in exactly the same manner as the cell whose state is to be sensed. In conventional read amplifier circuits this comparison is performed by using current/voltage (I/V) converters. These converters are formed by current mirrors using P-channel transistors.
Read amplifier circuits are therefore often based on a current mirror between two branches, as shown in FIG. 1. This figure shows how the drain terminals of the reference memory cells 1 and 2 are connected to a bit line and a decoder selects one of them. One circuit is connected to the bit line of the selected cell and at the same time a similar circuit is connected to the virgin cell located external the cell array, or to the reference memory cells depending on the situation.
The resulting two different currents are usually mirrored on PMOS transistors and are converted into voltages by a current/voltage converter which is formed using PMOS transistors. The resulting voltages, designated in FIG. 1 by Vref and Vcell, are applied to the inputs of a differential comparator 3. The differential comparator 3 compares the two voltages and provides at an output a logic value related to the state of the memory cell being considered.
The approach shown in FIG. 1 can have limitations when the supply voltage Vdd drops to approximately 1.8 V due to the presence of the diode-connected PMOS transistor. The speed of the read amplifier circuit of FIG. 1 is further greatly influenced by the reference current. When the reference current tends to become very low the amplifier circuit accordingly tends to become very slow.
Therefore, a drawback of conventional read amplifier circuits is that they are unable to discriminate very low currents while maintaining good speed and functionality characteristics even at supply voltages below 2 V. Moreover, conventional read amplifier circuits are unable to operate over a wide range of supply voltages. This characteristic would be highly desirable for applications in so-called smart cards, for example.